[PATCH] D157847: [RISCV] Fix assertion when passing f64 vectors via integer registers

Alex Bradbury via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 14 03:47:29 PDT 2023

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asb added a comment.

Oh, and please add "Fixes #64645" or similar to the commit message.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157847/new/

https://reviews.llvm.org/D157847

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