[PATCH] D157847: [RISCV] Fix assertion when passing f64 vectors via integer registers

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/pr64645.ll:8
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ret
+  ret <2 x double> %x
----------------
I have a question, do I need to load and store from the stack here?
```
eg:
        lw      a2, 12(a1)
        lw      a3, 8(a1)
        lw      a4, 4(a1)
        lw      a1, 0(a1)
        sw      a2, 12(a0)
        sw      a3, 8(a0)
        sw      a4, 4(a0)
        sw      a1, 0(a0)
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157847/new/

https://reviews.llvm.org/D157847