[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4147
+  // unable to detect as a splat during pattern matching. So directly lower it
+  // to a vmv.v.x gets picked up and matched to a vror.vi.
+  MVT ContainerVT = getContainerForFixedLengthVector(DAG, RotateVT, Subtarget);
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`So directly lower it to a vmv.v.x gets picked up and matched to a vror.vi.`

I think there's some words missing from that sentence.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157417/new/

https://reviews.llvm.org/D157417