[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 548548.
luke added a comment.

Fix typo in comments
Also move logic from ShuffleVectorSDNode to ShuffleVectorInst in 
Instruction.h. The old signature returned an EVT since nothing else in 
SelectionDAGNodes.h seemed to return an MVT, but we still had to pass 
through an MVT which seemed hairy. So I've shuffled it about to just 
operate on the mask array and placed it amongst the other mask helpers, 
even though it isn't necessarily used by the middle-end. But I think that 
should be OK, since the helpers in ShuffleVectorInst are used by both the 
middle-end and the backend.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157417/new/

https://reviews.llvm.org/D157417

Files:
  llvm/include/llvm/IR/Instructions.h
  llvm/lib/IR/Instructions.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

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