[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4141-4147
+  // If we just create the shift amount with
+  //
+  // DAG.getConstant(RotateAmt, DL, RotateVT)
+  //
+  // then for e64 we get a weird bitcasted build_vector on RV32 that we're
+  // unable to detect as a splat during pattern matching. So directly lower it
+  // to a vmv.v.x gets picked up and matched to a vror.vi.
----------------
As an example, If the rotateAmt is 24 then on RV32 the constant comes out as:

```
t3:v1i64 = bitcast t4
t4:v2i32 = build_vector <i32 24, i32 0>
```

I tried handling this case in lowerBuildVectorOfConstants to lower it as a v1i64 vmv_v_x_vl, with the constant reinterpreted across the elements, but it doesn't seem to catch any other cases since this pattern doesn't seem to be generated anywhere else. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157417/new/

https://reviews.llvm.org/D157417