[PATCH] D157077: [RISCV] Teach VSETVLIInserter to not demand tail policy when there is no tail element

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan updated this revision to Diff 548050.
jacquesguan marked 2 inline comments as done.
jacquesguan added a comment.

change switch to equal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157077/new/

https://reviews.llvm.org/D157077

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

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