[PATCH] D157077: [RISCV] Teach VSETVLIInserter to not demand tail policy when there is no tail element

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll:585
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, tu, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8, v0.t
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Wouldn't we want ta instead of tu since there is no tail?


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https://reviews.llvm.org/D157077