[PATCH] D156926: [RISCV] Add bf16 to isFPImmLegal.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa8c502a58939: [RISCV] Add bf16 to isFPImmLegal. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D156926?vs=546557&id=546891#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156926/new/

https://reviews.llvm.org/D156926

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/bfloat-imm.ll
  llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll


Index: llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
+++ llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
@@ -178,11 +178,8 @@
 ; CHECK-LABEL: select_icmp_slt_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    slti a0, a0, 1
-; CHECK-NEXT:    slli a0, a0, 1
-; CHECK-NEXT:    lui a1, %hi(.LCPI10_0)
-; CHECK-NEXT:    addi a1, a1, %lo(.LCPI10_0)
-; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    flh fa0, 0(a0)
+; CHECK-NEXT:    fcvt.s.w fa5, a0
+; CHECK-NEXT:    fcvt.bf16.s fa0, fa5
 ; CHECK-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, bfloat 1.000000e+00, bfloat 0.000000e+00
@@ -192,12 +189,9 @@
 define bfloat @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    slli a0, a0, 1
-; CHECK-NEXT:    lui a1, %hi(.LCPI11_0)
-; CHECK-NEXT:    addi a1, a1, %lo(.LCPI11_0)
-; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    flh fa0, 0(a0)
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.s.w fa5, a0
+; CHECK-NEXT:    fcvt.bf16.s fa0, fa5
 ; CHECK-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, bfloat 0.000000e+00, bfloat 1.000000e+00
Index: llvm/test/CodeGen/RISCV/bfloat-imm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/bfloat-imm.ll
+++ llvm/test/CodeGen/RISCV/bfloat-imm.ll
@@ -29,8 +29,7 @@
 define bfloat @bfloat_zero() nounwind {
 ; CHECK-LABEL: bfloat_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(.LCPI2_0)
-; CHECK-NEXT:    flh fa0, %lo(.LCPI2_0)(a0)
+; CHECK-NEXT:    fmv.h.x fa0, zero
 ; CHECK-NEXT:    ret
   ret bfloat 0.0
 }
@@ -38,8 +37,8 @@
 define bfloat @bfloat_negative_zero() nounwind {
 ; CHECK-LABEL: bfloat_negative_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT:    flh fa0, %lo(.LCPI3_0)(a0)
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    fmv.h.x fa0, a0
 ; CHECK-NEXT:    ret
   ret bfloat -0.0
 }
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1909,6 +1909,8 @@
     IsLegalVT = Subtarget.hasStdExtFOrZfinx();
   else if (VT == MVT::f64)
     IsLegalVT = Subtarget.hasStdExtDOrZdinx();
+  else if (VT == MVT::bf16)
+    IsLegalVT = Subtarget.hasStdExtZfbfmin();
 
   if (!IsLegalVT)
     return false;
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -876,6 +876,10 @@
     switch (VT.SimpleTy) {
     default:
       llvm_unreachable("Unexpected size");
+    case MVT::bf16:
+      assert(Subtarget->hasStdExtZfbfmin());
+      Opc = RISCV::FMV_H_X;
+      break;
     case MVT::f16:
       Opc =
           Subtarget->hasStdExtZhinxOrZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X;


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