[PATCH] D156939: [AMDGPU][True16] Support disassembling .h registers.

[Joe Nash via Phabricator via llvm-commits]

Joe_Nash requested changes to this revision.
Joe_Nash added a comment.
This revision now requires changes to proceed.

The hi/lo bit was specifically chosen to be the LSB in the Register encoding so that subtracting registers creates a logical register range. This is used for True16 codegen support SIInsertWaitcnts, and likely elsewhere.
I do not think it is a good idea to introduce changes while upstreaming the feature because they cannot be tested against the codegen implementation downstream. There is not enough context for code inspection or test coverage upstream to support whether that bit layout change is a good idea.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156939/new/

https://reviews.llvm.org/D156939