[llvm] 4dcf687 - [X86] combineAnd - limit and(extract_vector_elt(shuffle(x)) -> extract_vector_elt(shuffle'(x)) fold to one use of the extract_vector_elt.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-03T10:20:20+01:00
New Revision: 4dcf6877b4bf1f72ff2326869d27a48287502758

URL: https://github.com/llvm/llvm-project/commit/4dcf6877b4bf1f72ff2326869d27a48287502758
DIFF: https://github.com/llvm/llvm-project/commit/4dcf6877b4bf1f72ff2326869d27a48287502758.diff

LOG: [X86] combineAnd - limit and(extract_vector_elt(shuffle(x)) -> extract_vector_elt(shuffle'(x)) fold to one use of the extract_vector_elt.

Prevents a regression in an upcoming patch.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 27015435583a9a..960688087cb996 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48370,7 +48370,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
   // Attempt to combine a scalar bitmask AND with an extracted shuffle.
   if ((VT.getScalarSizeInBits() % 8) == 0 &&
       N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
-      isa<ConstantSDNode>(N0.getOperand(1))) {
+      isa<ConstantSDNode>(N0.getOperand(1)) && N0->hasOneUse()) {
     SDValue BitMask = N1;
     SDValue SrcVec = N0.getOperand(0);
     EVT SrcVecVT = SrcVec.getValueType();