[llvm] 7f9b94c - [X86] LowerBuildVectorv16i8 - attempt to merge lowest 2 x i16 insertions into a i32 MOVD scalar_to_vectpr
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 3 02:20:32 PDT 2023
Author: Simon Pilgrim
Date: 2023-08-03T10:20:20+01:00
New Revision: 7f9b94c0445d92e44ee97d5300ac1657570f7bd9
URL: https://github.com/llvm/llvm-project/commit/7f9b94c0445d92e44ee97d5300ac1657570f7bd9
DIFF: https://github.com/llvm/llvm-project/commit/7f9b94c0445d92e44ee97d5300ac1657570f7bd9.diff
LOG: [X86] LowerBuildVectorv16i8 - attempt to merge lowest 2 x i16 insertions into a i32 MOVD scalar_to_vectpr
Similar to D156350, if we were going to create 2 x i16 insertions (MOVD+PINSRW), try to merge them into a single MOVD to reduce the amount of GPR<->VEC traffic
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/buildvec-insertvec.ll
llvm/test/CodeGen/X86/extract-concat.ll
llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
llvm/test/CodeGen/X86/promote-vec3.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2aed22c8778389..27015435583a9a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -6258,13 +6258,29 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, const APInt &NonZeroMask,
SDValue V;
// Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
- for (unsigned i = 0; i < 16; i += 2) {
+ // If both the lowest 16-bits are non-zero, then convert to MOVD.
+ if (!NonZeroMask.extractBits(2, 0).isZero() &&
+ !NonZeroMask.extractBits(2, 2).isZero()) {
+ for (unsigned I = 0; I != 4; ++I) {
+ if (!NonZeroMask[I])
+ continue;
+ SDValue Elt = DAG.getZExtOrTrunc(Op.getOperand(I), dl, MVT::i32);
+ if (I != 0)
+ Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
+ DAG.getConstant(I * 8, dl, MVT::i8));
+ V = V ? DAG.getNode(ISD::OR, dl, MVT::i32, V, Elt) : Elt;
+ }
+ assert(V && "Failed to fold v16i8 vector to zero");
+ V = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, V);
+ V = DAG.getNode(X86ISD::VZEXT_MOVL, dl, MVT::v4i32, V);
+ V = DAG.getBitcast(MVT::v8i16, V);
+ }
+ for (unsigned i = V ? 4 : 0; i < 16; i += 2) {
bool ThisIsNonZero = NonZeroMask[i];
bool NextIsNonZero = NonZeroMask[i + 1];
if (!ThisIsNonZero && !NextIsNonZero)
continue;
- // FIXME: Investigate combining the first 4 bytes as a i32 instead.
SDValue Elt;
if (ThisIsNonZero) {
if (NumZero || NextIsNonZero)
diff --git a/llvm/test/CodeGen/X86/buildvec-insertvec.ll b/llvm/test/CodeGen/X86/buildvec-insertvec.ll
index e1f139c66db953..2e846f900efcd7 100644
--- a/llvm/test/CodeGen/X86/buildvec-insertvec.ll
+++ b/llvm/test/CodeGen/X86/buildvec-insertvec.ll
@@ -10,14 +10,14 @@ define void @foo(<3 x float> %in, ptr nocapture %out) nounwind {
; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-NEXT: shll $8, %ecx
; SSE2-NEXT: orl %eax, %ecx
-; SSE2-NEXT: movd %ecx, %xmm0
-; SSE2-NEXT: movl $65280, %eax # imm = 0xFF00
-; SSE2-NEXT: orl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: pinsrw $1, %eax, %xmm0
-; SSE2-NEXT: movd %xmm0, (%rdi)
+; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: shll $16, %eax
+; SSE2-NEXT: orl %ecx, %eax
+; SSE2-NEXT: orl $-16777216, %eax # imm = 0xFF000000
+; SSE2-NEXT: movl %eax, (%rdi)
; SSE2-NEXT: retq
;
; SSE41-LABEL: foo:
diff --git a/llvm/test/CodeGen/X86/extract-concat.ll b/llvm/test/CodeGen/X86/extract-concat.ll
index 8eb68d3f76696b..d2310aba0e3f48 100644
--- a/llvm/test/CodeGen/X86/extract-concat.ll
+++ b/llvm/test/CodeGen/X86/extract-concat.ll
@@ -11,14 +11,14 @@ define void @foo(<4 x float> %in, ptr %out) {
; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-NEXT: shll $8, %ecx
; SSE2-NEXT: orl %eax, %ecx
-; SSE2-NEXT: movd %ecx, %xmm0
-; SSE2-NEXT: movl $65280, %eax # imm = 0xFF00
-; SSE2-NEXT: orl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: pinsrw $1, %eax, %xmm0
-; SSE2-NEXT: movd %xmm0, (%rdi)
+; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: shll $16, %eax
+; SSE2-NEXT: orl %ecx, %eax
+; SSE2-NEXT: orl $-16777216, %eax # imm = 0xFF000000
+; SSE2-NEXT: movl %eax, (%rdi)
; SSE2-NEXT: retq
;
; SSE42-LABEL: foo:
diff --git a/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll b/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
index d156239efee664..5cd9281929a32b 100644
--- a/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
+++ b/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
@@ -60,39 +60,41 @@ define <4 x i1> @test_signed_v4i1_v4f32(<4 x float> %f) nounwind {
define <4 x i8> @test_signed_v4i8_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i8_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; CHECK-NEXT: movaps %xmm2, %xmm3
-; CHECK-NEXT: maxss %xmm1, %xmm3
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: movaps %xmm1, %xmm4
+; CHECK-NEXT: movaps %xmm1, %xmm3
+; CHECK-NEXT: maxss %xmm0, %xmm3
+; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: movaps %xmm2, %xmm4
; CHECK-NEXT: minss %xmm3, %xmm4
; CHECK-NEXT: cvttss2si %xmm4, %eax
-; CHECK-NEXT: shll $8, %eax
+; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movaps %xmm0, %xmm3
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
-; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
+; CHECK-NEXT: movaps %xmm1, %xmm4
; CHECK-NEXT: maxss %xmm3, %xmm4
-; CHECK-NEXT: movaps %xmm1, %xmm3
+; CHECK-NEXT: movaps %xmm2, %xmm3
; CHECK-NEXT: minss %xmm4, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %ecx
; CHECK-NEXT: movzbl %cl, %ecx
+; CHECK-NEXT: shll $8, %ecx
; CHECK-NEXT: orl %eax, %ecx
-; CHECK-NEXT: movaps %xmm2, %xmm3
-; CHECK-NEXT: maxss %xmm0, %xmm3
+; CHECK-NEXT: movaps %xmm0, %xmm3
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; CHECK-NEXT: movaps %xmm1, %xmm4
-; CHECK-NEXT: minss %xmm3, %xmm4
-; CHECK-NEXT: cvttss2si %xmm4, %eax
+; CHECK-NEXT: maxss %xmm3, %xmm4
+; CHECK-NEXT: movaps %xmm2, %xmm3
+; CHECK-NEXT: minss %xmm4, %xmm3
+; CHECK-NEXT: cvttss2si %xmm3, %eax
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: maxss %xmm0, %xmm2
-; CHECK-NEXT: minss %xmm2, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %edx
-; CHECK-NEXT: shll $8, %edx
-; CHECK-NEXT: orl %eax, %edx
-; CHECK-NEXT: movd %edx, %xmm0
-; CHECK-NEXT: pinsrw $1, %ecx, %xmm0
+; CHECK-NEXT: shll $16, %eax
+; CHECK-NEXT: orl %ecx, %eax
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: maxss %xmm0, %xmm1
+; CHECK-NEXT: minss %xmm1, %xmm2
+; CHECK-NEXT: cvttss2si %xmm2, %ecx
+; CHECK-NEXT: shll $24, %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i8> @llvm.fptosi.sat.v4i8.v4f32(<4 x float> %f)
ret <4 x i8> %x
@@ -669,11 +671,12 @@ define <8 x i8> @test_signed_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r15
; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: subq $32, %rsp
+; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: psrlq $48, %xmm0
+; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %r12d
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -687,7 +690,7 @@ define <8 x i8> @test_signed_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: cmovpl %r14d, %r12d
; CHECK-NEXT: shll $8, %r12d
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -718,24 +721,24 @@ define <8 x i8> @test_signed_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: cmoval %ebp, %eax
; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpl %r14d, %eax
-; CHECK-NEXT: shll $8, %eax
-; CHECK-NEXT: orl %r12d, %eax
-; CHECK-NEXT: movd %eax, %xmm0
-; CHECK-NEXT: pinsrw $1, %r15d, %xmm0
-; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: movzbl %al, %r13d
+; CHECK-NEXT: shll $8, %r13d
+; CHECK-NEXT: orl %r12d, %r13d
+; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: callq __extendhfsf2 at PLT
-; CHECK-NEXT: cvttss2si %xmm0, %r15d
+; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: cmovbl %ebx, %r15d
+; CHECK-NEXT: cmovbl %ebx, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: cmoval %ebp, %r15d
+; CHECK-NEXT: cmoval %ebp, %eax
; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: cmovpl %r14d, %r15d
-; CHECK-NEXT: shll $8, %r15d
-; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: movzbl %al, %r12d
+; CHECK-NEXT: shll $16, %r12d
+; CHECK-NEXT: orl %r13d, %r12d
+; CHECK-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: psrlq $48, %xmm0
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -744,10 +747,10 @@ define <8 x i8> @test_signed_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: cmoval %ebp, %eax
; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpl %r14d, %eax
-; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: orl %r15d, %eax
-; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: pinsrw $2, %eax, %xmm0
+; CHECK-NEXT: shll $24, %eax
+; CHECK-NEXT: orl %r12d, %eax
+; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: pinsrw $2, %r15d, %xmm0
; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
@@ -774,9 +777,10 @@ define <8 x i8> @test_signed_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: orl %r15d, %eax
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: pinsrw $3, %eax, %xmm0
-; CHECK-NEXT: addq $32, %rsp
+; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll b/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
index 7c053d2dad5086..0cced636dddbab 100644
--- a/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
+++ b/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
@@ -51,39 +51,41 @@ define <4 x i1> @test_unsigned_v4i1_v4f32(<4 x float> %f) nounwind {
define <4 x i8> @test_unsigned_v4i8_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_unsigned_v4i8_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: xorps %xmm3, %xmm3
-; CHECK-NEXT: maxss %xmm1, %xmm3
-; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: movaps %xmm1, %xmm4
+; CHECK-NEXT: maxss %xmm0, %xmm3
+; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: movaps %xmm2, %xmm4
; CHECK-NEXT: minss %xmm3, %xmm4
; CHECK-NEXT: cvttss2si %xmm4, %eax
-; CHECK-NEXT: shll $8, %eax
+; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movaps %xmm0, %xmm3
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
; CHECK-NEXT: xorps %xmm4, %xmm4
; CHECK-NEXT: maxss %xmm3, %xmm4
-; CHECK-NEXT: movaps %xmm1, %xmm3
+; CHECK-NEXT: movaps %xmm2, %xmm3
; CHECK-NEXT: minss %xmm4, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %ecx
; CHECK-NEXT: movzbl %cl, %ecx
+; CHECK-NEXT: shll $8, %ecx
; CHECK-NEXT: orl %eax, %ecx
-; CHECK-NEXT: xorps %xmm3, %xmm3
-; CHECK-NEXT: maxss %xmm0, %xmm3
-; CHECK-NEXT: movaps %xmm1, %xmm4
-; CHECK-NEXT: minss %xmm3, %xmm4
-; CHECK-NEXT: cvttss2si %xmm4, %eax
+; CHECK-NEXT: movaps %xmm0, %xmm3
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: maxss %xmm3, %xmm4
+; CHECK-NEXT: movaps %xmm2, %xmm3
+; CHECK-NEXT: minss %xmm4, %xmm3
+; CHECK-NEXT: cvttss2si %xmm3, %eax
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: maxss %xmm0, %xmm2
-; CHECK-NEXT: minss %xmm2, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %edx
-; CHECK-NEXT: shll $8, %edx
-; CHECK-NEXT: orl %eax, %edx
-; CHECK-NEXT: movd %edx, %xmm0
-; CHECK-NEXT: pinsrw $1, %ecx, %xmm0
+; CHECK-NEXT: shll $16, %eax
+; CHECK-NEXT: orl %ecx, %eax
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: maxss %xmm0, %xmm1
+; CHECK-NEXT: minss %xmm1, %xmm2
+; CHECK-NEXT: cvttss2si %xmm2, %ecx
+; CHECK-NEXT: shll $24, %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i8> @llvm.fptoui.sat.v4i8.v4f32(<4 x float> %f)
ret <4 x i8> %x
@@ -652,10 +654,11 @@ define <8 x i8> @test_unsigned_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r15
; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: subq $40, %rsp
+; CHECK-NEXT: subq $32, %rsp
; CHECK-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: psrlq $48, %xmm0
+; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %r15d
; CHECK-NEXT: xorl %ebx, %ebx
@@ -667,7 +670,7 @@ define <8 x i8> @test_unsigned_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: cmoval %ebp, %r15d
; CHECK-NEXT: shll $8, %r15d
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -692,32 +695,32 @@ define <8 x i8> @test_unsigned_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: cmovbl %ebx, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: cmoval %ebp, %eax
-; CHECK-NEXT: shll $8, %eax
-; CHECK-NEXT: orl %r15d, %eax
-; CHECK-NEXT: movd %eax, %xmm0
-; CHECK-NEXT: pinsrw $1, %r14d, %xmm0
-; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: movzbl %al, %r12d
+; CHECK-NEXT: shll $8, %r12d
+; CHECK-NEXT: orl %r15d, %r12d
+; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: callq __extendhfsf2 at PLT
-; CHECK-NEXT: cvttss2si %xmm0, %r14d
+; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: cmovbl %ebx, %r14d
+; CHECK-NEXT: cmovbl %ebx, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: cmoval %ebp, %r14d
-; CHECK-NEXT: shll $8, %r14d
-; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: movzbl %al, %r15d
+; CHECK-NEXT: shll $16, %r15d
+; CHECK-NEXT: orl %r12d, %r15d
+; CHECK-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: psrlq $48, %xmm0
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: cmovbl %ebx, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: cmoval %ebp, %eax
-; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: orl %r14d, %eax
-; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: pinsrw $2, %eax, %xmm0
+; CHECK-NEXT: shll $24, %eax
+; CHECK-NEXT: orl %r15d, %eax
+; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: pinsrw $2, %r14d, %xmm0
; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
@@ -740,8 +743,9 @@ define <8 x i8> @test_unsigned_v8i8_v8f16(<8 x half> %f) nounwind {
; CHECK-NEXT: orl %r14d, %eax
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: pinsrw $3, %eax, %xmm0
-; CHECK-NEXT: addq $40, %rsp
+; CHECK-NEXT: addq $32, %rsp
; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
diff --git a/llvm/test/CodeGen/X86/promote-vec3.ll b/llvm/test/CodeGen/X86/promote-vec3.ll
index 482db62c437108..f28a2ad0fd009a 100644
--- a/llvm/test/CodeGen/X86/promote-vec3.ll
+++ b/llvm/test/CodeGen/X86/promote-vec3.ll
@@ -8,9 +8,9 @@
define <3 x i16> @zext_i8(<3 x i8>) {
; SSE3-LABEL: zext_i8:
; SSE3: # %bb.0:
+; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; SSE3-NEXT: # kill: def $ax killed $ax killed $eax
; SSE3-NEXT: # kill: def $dx killed $dx killed $edx
; SSE3-NEXT: # kill: def $cx killed $cx killed $ecx
@@ -58,12 +58,12 @@ define <3 x i16> @zext_i8(<3 x i8>) {
define <3 x i16> @sext_i8(<3 x i8>) {
; SSE3-LABEL: sext_i8:
; SSE3: # %bb.0:
-; SSE3-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE3-NEXT: shll $8, %eax
+; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; SSE3-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; SSE3-NEXT: shll $8, %ecx
-; SSE3-NEXT: movd %ecx, %xmm0
-; SSE3-NEXT: pinsrw $1, %eax, %xmm0
+; SSE3-NEXT: shll $24, %ecx
+; SSE3-NEXT: shll $8, %eax
+; SSE3-NEXT: orl %ecx, %eax
+; SSE3-NEXT: movd %eax, %xmm0
; SSE3-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE3-NEXT: shll $8, %eax
; SSE3-NEXT: pinsrw $2, %eax, %xmm0
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