[PATCH] D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6101
     if (CC != ISD::SETCC_INVALID) {
-      unsigned NewOpcode;
+      std::optional<unsigned> NewOpcode;
       bool IsSigned = isSignedIntSetCC(CC);
----------------
arsenm wrote:
> might as well use 0 for invalid opcode
I think we often use ISD::DELETED_NODE which I think is 0.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6158
+                    (LogicOp->getOpcode() == ISD::AND)))
+            NewOpcode = isNotSNaN ? std::optional<unsigned>(ISD::FMAXNUM_IEEE)
+                                  : isFMINNUM_FMAXNUM_Supported
----------------
arsenm wrote:
> i think the optional makes this noisier, just use 0 or instruction_list_end as the sentinel 
This is ISD so we shouln't use instruction_list_end, but ISD::DELETED_NODE would work.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155267/new/

https://reviews.llvm.org/D155267