[PATCH] D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 2 15:16:39 PDT 2023
arsenm added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6101
if (CC != ISD::SETCC_INVALID) {
- unsigned NewOpcode;
+ std::optional<unsigned> NewOpcode;
bool IsSigned = isSignedIntSetCC(CC);
----------------
might as well use 0 for invalid opcode
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6112-6162
+ // The optimization cannot be applied for all the predicates because
+ // of the way FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle
+ // NaNs. For FMINNUM_IEEE/FMAXNUM_IEEE, the optimization cannot be
+ // applied at all if one of the operands is a signaling NaN.
+ bool isNotNaN =
+ DAG.isKnownNeverNaN(Operand1) && DAG.isKnownNeverNaN(Operand2);
+ bool isNotSNaN =
----------------
Can you move this all to a helper function? It would be easier to read with early exits. Plus you can defer the isKnownNeverSNan calls depend on whether the legality more easily
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6158
+ (LogicOp->getOpcode() == ISD::AND)))
+ NewOpcode = isNotSNaN ? std::optional<unsigned>(ISD::FMAXNUM_IEEE)
+ : isFMINNUM_FMAXNUM_Supported
----------------
i think the optional makes this noisier, just use 0 or instruction_list_end as the sentinel
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155267/new/
https://reviews.llvm.org/D155267
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