[llvm] 5a51996 - [RISCV] Call combineSelectToBinOp before generic select expansion for Zicond.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 1 12:09:57 PDT 2023
Author: Craig Topper
Date: 2023-08-01T12:09:35-07:00
New Revision: 5a519961c8113c4ddcb3627c2366c2291c97624f
URL: https://github.com/llvm/llvm-project/commit/5a519961c8113c4ddcb3627c2366c2291c97624f
DIFF: https://github.com/llvm/llvm-project/commit/5a519961c8113c4ddcb3627c2366c2291c97624f.diff
LOG: [RISCV] Call combineSelectToBinOp before generic select expansion for Zicond.
This handles logical ops of setccs and optimizes when the true or
false value is -1.
Reviewed By: asb, wangpc
Differential Revision: https://reviews.llvm.org/D156810
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/select-binop-identity.ll
llvm/test/CodeGen/RISCV/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f5f72b36afa372..9d38d01691ddec 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6071,6 +6071,10 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
ISD::OR, DL, VT, FalseV,
DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV));
+ // Try some other optimizations before falling back to generic lowering.
+ if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))
+ return V;
+
// (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
return DAG.getNode(ISD::OR, DL, VT,
DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll
index ef2f866e0edec6..ebf47cdfd2a1d3 100644
--- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll
+++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=SFB64 %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=VTCONDOPS64 %s
+; RUN: | FileCheck -check-prefixes=RV64,VTCONDOPS64 %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=ZICOND,ZICOND32 %s
+; RUN: | FileCheck -check-prefixes=RV32,ZICOND,ZICOND32 %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=ZICOND,ZICOND64 %s
+; RUN: | FileCheck -check-prefixes=RV64,ZICOND,ZICOND64 %s
; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for
; other binary operations using their identity value as the constant.
@@ -19,19 +19,19 @@
; the basic block we create when we expand select.
define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
-; RV32I-LABEL: and_select_all_ones_i32:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: and_select_all_ones_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: ret
+; RV32-LABEL: and_select_all_ones_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: or a0, a0, a1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: and_select_all_ones_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: or a0, a0, a1
+; RV64-NEXT: and a0, a0, a2
+; RV64-NEXT: ret
;
; SFB64-LABEL: and_select_all_ones_i32:
; SFB64: # %bb.0:
@@ -41,45 +41,27 @@ define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 s
; SFB64-NEXT: .LBB0_2:
; SFB64-NEXT: mv a0, a2
; SFB64-NEXT: ret
-;
-; VTCONDOPS64-LABEL: and_select_all_ones_i32:
-; VTCONDOPS64: # %bb.0:
-; VTCONDOPS64-NEXT: li a3, -1
-; VTCONDOPS64-NEXT: vt.maskcn a3, a3, a0
-; VTCONDOPS64-NEXT: vt.maskc a0, a1, a0
-; VTCONDOPS64-NEXT: or a0, a0, a3
-; VTCONDOPS64-NEXT: and a0, a0, a2
-; VTCONDOPS64-NEXT: ret
-;
-; ZICOND-LABEL: and_select_all_ones_i32:
-; ZICOND: # %bb.0:
-; ZICOND-NEXT: li a3, -1
-; ZICOND-NEXT: czero.nez a3, a3, a0
-; ZICOND-NEXT: czero.eqz a0, a1, a0
-; ZICOND-NEXT: or a0, a0, a3
-; ZICOND-NEXT: and a0, a0, a2
-; ZICOND-NEXT: ret
%a = select i1 %c, i32 %x, i32 -1
%b = and i32 %a, %y
ret i32 %b
}
define i64 @and_select_all_ones_i64(i1 zeroext %c, i64 %x, i64 %y) {
-; RV32I-LABEL: and_select_all_ones_i64:
-; RV32I: # %bb.0:
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: or a2, a0, a2
-; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: and a0, a3, a0
-; RV32I-NEXT: and a1, a4, a2
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: and_select_all_ones_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: and a0, a2, a0
-; RV64I-NEXT: ret
+; RV32-LABEL: and_select_all_ones_i64:
+; RV32: # %bb.0:
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: or a2, a0, a2
+; RV32-NEXT: or a0, a0, a1
+; RV32-NEXT: and a0, a3, a0
+; RV32-NEXT: and a1, a4, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: and_select_all_ones_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: or a0, a0, a1
+; RV64-NEXT: and a0, a2, a0
+; RV64-NEXT: ret
;
; SFB64-LABEL: and_select_all_ones_i64:
; SFB64: # %bb.0:
@@ -89,36 +71,6 @@ define i64 @and_select_all_ones_i64(i1 zeroext %c, i64 %x, i64 %y) {
; SFB64-NEXT: .LBB1_2:
; SFB64-NEXT: mv a0, a2
; SFB64-NEXT: ret
-;
-; VTCONDOPS64-LABEL: and_select_all_ones_i64:
-; VTCONDOPS64: # %bb.0:
-; VTCONDOPS64-NEXT: vt.maskcn a1, a1, a0
-; VTCONDOPS64-NEXT: li a3, -1
-; VTCONDOPS64-NEXT: vt.maskc a0, a3, a0
-; VTCONDOPS64-NEXT: or a0, a0, a1
-; VTCONDOPS64-NEXT: and a0, a2, a0
-; VTCONDOPS64-NEXT: ret
-;
-; ZICOND32-LABEL: and_select_all_ones_i64:
-; ZICOND32: # %bb.0:
-; ZICOND32-NEXT: czero.nez a2, a2, a0
-; ZICOND32-NEXT: li a5, -1
-; ZICOND32-NEXT: czero.eqz a5, a5, a0
-; ZICOND32-NEXT: or a2, a5, a2
-; ZICOND32-NEXT: czero.nez a0, a1, a0
-; ZICOND32-NEXT: or a0, a5, a0
-; ZICOND32-NEXT: and a0, a3, a0
-; ZICOND32-NEXT: and a1, a4, a2
-; ZICOND32-NEXT: ret
-;
-; ZICOND64-LABEL: and_select_all_ones_i64:
-; ZICOND64: # %bb.0:
-; ZICOND64-NEXT: czero.nez a1, a1, a0
-; ZICOND64-NEXT: li a3, -1
-; ZICOND64-NEXT: czero.eqz a0, a3, a0
-; ZICOND64-NEXT: or a0, a0, a1
-; ZICOND64-NEXT: and a0, a2, a0
-; ZICOND64-NEXT: ret
%a = select i1 %c, i64 -1, i64 %x
%b = and i64 %y, %a
ret i64 %b
diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
index 6786f440e713c4..754237c3456dc0 100644
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -5670,9 +5670,7 @@ define zeroext i1 @uaddo.i64.constant(i64 %v1, ptr %res) {
; RV32ZICOND-NEXT: sltu a0, a3, a0
; RV32ZICOND-NEXT: add a4, a1, a0
; RV32ZICOND-NEXT: sltu a1, a4, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT: czero.nez a0, a0, a0
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: and a0, a0, a1
; RV32ZICOND-NEXT: sw a3, 0(a2)
; RV32ZICOND-NEXT: sw a4, 4(a2)
; RV32ZICOND-NEXT: ret
@@ -5739,9 +5737,7 @@ define zeroext i1 @uaddo.i64.constant_2048(i64 %v1, ptr %res) {
; RV32ZICOND-NEXT: sltu a0, a3, a0
; RV32ZICOND-NEXT: add a4, a1, a0
; RV32ZICOND-NEXT: sltu a1, a4, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT: czero.nez a0, a0, a0
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: and a0, a0, a1
; RV32ZICOND-NEXT: sw a3, 0(a2)
; RV32ZICOND-NEXT: sw a4, 4(a2)
; RV32ZICOND-NEXT: ret
@@ -5809,9 +5805,7 @@ define zeroext i1 @uaddo.i64.constant_2049(i64 %v1, ptr %res) {
; RV32ZICOND-NEXT: sltu a0, a3, a0
; RV32ZICOND-NEXT: add a4, a1, a0
; RV32ZICOND-NEXT: sltu a1, a4, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT: czero.nez a0, a0, a0
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: and a0, a0, a1
; RV32ZICOND-NEXT: sw a3, 0(a2)
; RV32ZICOND-NEXT: sw a4, 4(a2)
; RV32ZICOND-NEXT: ret
@@ -5892,9 +5886,7 @@ define i64 @uaddo.i64.constant_setcc_on_overflow_flag(ptr %p) {
; RV32ZICOND-NEXT: sltu a3, a0, a1
; RV32ZICOND-NEXT: add a1, a2, a3
; RV32ZICOND-NEXT: sltu a2, a1, a2
-; RV32ZICOND-NEXT: czero.eqz a2, a2, a3
-; RV32ZICOND-NEXT: czero.nez a3, a3, a3
-; RV32ZICOND-NEXT: or a2, a3, a2
+; RV32ZICOND-NEXT: and a2, a3, a2
; RV32ZICOND-NEXT: bnez a2, .LBB69_2
; RV32ZICOND-NEXT: # %bb.1: # %IfOverflow
; RV32ZICOND-NEXT: li a0, 0
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