[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types that are a power of 2

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj updated this revision to Diff 546171.
nitinjohnraj added a comment.

Added rules for G_SEXT_INREG. Now this patch works for non-pow 2 types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155772/new/

https://reviews.llvm.org/D155772

Files:
  llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir

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