[PATCH] D156538: [AArch64] Try to combine FMUL with FDIV

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added a comment.

In D156538#4550702 <https://reviews.llvm.org/D156538#4550702>, @samtebbs wrote:

> I think this is good as it is, although I'm not 100% sure on the fact that we need to get it converted to `aarch64_neon_vcvtfxs2fp` first, as if something goes wrong there then we'll miss out on this optimisation. If you can think of a way to circumvent the need for that and go directly to the scvtf that would be good, otherwise this looks good to me.

Thanks for comment.
There is a comment in `AArch64InstrInfo.td` as below and it looks there was TableGen issue to generate the simd type instruction directly.

  defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
  defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
  defm SCVTF  : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
  defm UCVTF  : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
  // Codegen patterns for the above. We don't put these directly on the
  // instructions because TableGen's type inference can't handle the truth.
  // Having the same base pattern for fp <--> int totally freaks it out.


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