[PATCH] D156801: [RISCV] Improve codegen for i8/i16 'atomicrmw xchg a, 0'
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 1 08:43:53 PDT 2023
craig.topper added inline comments.
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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16730
Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
+ // In the case of an atomicrmw xchg with a constant 0 operand, replace the
+ // atomic instruction with an AtomicRMWInst::And with appropriate mask, as
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We can also support -1 using amoor.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D156801/new/
https://reviews.llvm.org/D156801
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