[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7135
+static inline bool isValidEGW(int EGS, EVT VT) {
+  return VT.getSizeInBits().getKnownMinValue() >= EGS * VT.getScalarSizeInBits();
+}
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Doesn't this need to consider the value of vscale or VLEN? getKnownMinValue() always returns 64 for <vscale x 2 x i32>.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:758
+                          (vti.Vector vti.RegClass:$rs2),
+                          (NegImm64 uimm6:$rs1),
+                          (vti.Mask V0),
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NegImm64 no longer exists. I changed it in https://reviews.llvm.org/D156348


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138809/new/

https://reviews.llvm.org/D138809