[PATCH] D156437: [RISCV] Fix the CFI offset for callee-saved registers stored by Zcmp push.

Mon Jul 31 02:40:01 PDT 2023

Jim added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:589
+        // .cfi_offset s0, -8 => .cfi_offset s0, -4
+        Offset = -(FrameIdx + RVFI->getRVPushRegs() + 1) *
+                 (int64_t)STI.getXLen() / 8;
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fakepaper56 wrote:
> The original code looks like we expect negative frame indices are related to their saved location.
> If we want to reserve the behavior of negative frame indices, I think we should have specific `hasReservedSpillSlot` behavior for `Zcmp`?
I am not sure does any other take care about the order of callee-saved register stored in memory except CFI offset.

RISCVRegisterInfo::hasReservedSpillSlot now is unable to get the total number of callee-saved register stored for calculating frame index in reverse order. I would try to pass extra parameter `number of callee-saved regsiter saved` to RISCVRegisterInfo::hasReservedSpillSlot.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156437/new/

https://reviews.llvm.org/D156437