[PATCH] D156642: libunwind: riscv: disable vector test when csr instructions aren't present

[Sean Cross via Phabricator via llvm-commits]

xobs updated this revision to Diff 545517.
xobs added a comment.

Change define gate from `__riscv_v` to `__riscv_zicsr`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156642/new/

https://reviews.llvm.org/D156642

Files:
  libunwind/src/Registers.hpp


Index: libunwind/src/Registers.hpp
===================================================================
--- libunwind/src/Registers.hpp
+++ libunwind/src/Registers.hpp
@@ -4101,11 +4101,13 @@
     return 0;
   if ((regNum > 0) && (regNum < 32))
     return _registers[regNum];
+#if defined(__riscv_zicsr)
   if (regNum == UNW_RISCV_VLENB) {
     reg_t vlenb;
     __asm__("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }
+#endif
   _LIBUNWIND_ABORT("unsupported riscv register");
 }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D156642.545517.patch
Type: text/x-patch
Size: 492 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230731/cdcf38ec/attachment.bin>