[PATCH] D156642: libunwind: riscv: disable vector test when csr instructions aren't present

[Sean Cross via Phabricator via llvm-commits]

xobs added a comment.

Thanks for the input! I didn't realise that clang was making an explicit choice to keep those instructions in the base ISA, which certainly explains why I haven't seen any issues in Rust, and why they haven't renamed all of the targets to include`_zicsr`.

Given all that, I think that the decision to check for the `__riscv_zicsr` gate is the correct choice, and I've updated the patch accordingly.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D156642/new/

https://reviews.llvm.org/D156642