[PATCH] D156319: [RISCV] Relax ta/ma policy into tu/mu in InsertVSETVLI

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added a comment.

I like the idea, but as @craig.topper says, this can be negative for OoO processors.
What about making this feature a SubtargetFeature and then processors can enable it depending on their implementation?
(and there won't be huge changes in tests)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D156319/new/

https://reviews.llvm.org/D156319