[PATCH] D156319: [RISCV] Relax ta/ma policy into tu/mu in InsertVSETVLI

Wed Jul 26 12:24:59 PDT 2023

luke planned changes to this revision.
luke added a comment.

In D156319#4535747 <https://reviews.llvm.org/D156319#4535747>, @craig.topper wrote:

> In D156319#4535006 <https://reviews.llvm.org/D156319#4535006>, @luke wrote:
>
>> This reduces the number of vsetvli toggles and improves code size at least, but I can't comment on the effect of undisturbed on register renaming etc.
>
> This can create false dependencies on out of order CPUs that will prevent instructions from being executed until the previous writer of their destination register has completed.

In D156319#4535952 <https://reviews.llvm.org/D156319#4535952>, @wangpc wrote:

> I like the idea, but as @craig.topper says, this can be negative for OoO processors.
> What about making this feature a SubtargetFeature and then processors can enable it depending on their implementation?
> (and there won't be huge changes in tests)

I thought there might be a caveat as such, thanks for the explanation. I don't have any specific subtarget in mind for this, so I'm happy to remove it off of the review queue for now. We can always pick it up later if there's an in order processor that could utilise it

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https://reviews.llvm.org/D156319