[PATCH] D156099: [AMDGPU] Add True16 register classes.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev marked an inline comment as done.
kosarev added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:1034
+def VS_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,
+                          (add VGPR_16, SReg_32, LDS_DIRECT_CLASS)> {
+  let isAllocatable = 0;
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rampitec wrote:
> Does this really work when you have an RC with registers of different size?
> Does this really work when you have an RC with registers of different size?

It seems so, yes. Downstream I see us generating instructions like `v_and_b16 v0.l, s2, v0.l` without problem.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D156099/new/

https://reviews.llvm.org/D156099