[PATCH] D156099: [AMDGPU] Add True16 register classes.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:1034
+def VS_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,
+                          (add VGPR_16, SReg_32, LDS_DIRECT_CLASS)> {
+  let isAllocatable = 0;
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Does this really work when you have an RC with registers of different size?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156099/new/

https://reviews.llvm.org/D156099