[PATCH] D156099: [AMDGPU] Add True16 register classes.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev marked 2 inline comments as done.
kosarev added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:594
   let GeneratePressureSet = 0;
-  let BaseClassOrder = 16;
+  let BaseClassOrder = 18;
 }
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foad wrote:
> Do VGPR_LO16 and VGPR_HI16 need to define BaseClassOrder? From the comments below it sounds like the base class of a 16-bit VGPR will always be VGPR_16_Lo128 or VGPR_16.
Indeed these are now base classes to no registers. Nice catch, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156099/new/

https://reviews.llvm.org/D156099