[PATCH] D156099: [AMDGPU] Add True16 register classes.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev updated this revision to Diff 543590.
kosarev added a comment.

Removed extra BaseClassOrder assignments and use Reg16Types.types instead of [i16, f16].


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156099/new/

https://reviews.llvm.org/D156099

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
  llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
  llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
  llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
  llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
  llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
  llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir

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