[PATCH] D156099: [AMDGPU] Add True16 register classes.

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:594
   let GeneratePressureSet = 0;
-  let BaseClassOrder = 16;
+  let BaseClassOrder = 18;
 }
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Do VGPR_LO16 and VGPR_HI16 need to define BaseClassOrder? From the comments below it sounds like the base class of a 16-bit VGPR will always be VGPR_16_Lo128 or VGPR_16.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:1035
 
+def VS_16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,
+                          (add VGPR_16, SReg_32, LDS_DIRECT_CLASS)> {
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Use `Reg16Types.types` here and below?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156099/new/

https://reviews.llvm.org/D156099