[PATCH] D155910: [RISCV] Support register allocation for GHC when f/d is not specified in the architecture

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Could you tweak the title / commit message though so it's clearer this is about an issue with zfinx/zdinx? Thanks.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155910/new/

https://reviews.llvm.org/D155910