[PATCH] D155910: [RISCV] Support register allocation for GHC when f/d is not specified in the architecture

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG78d91df452d6: [RISCV] Support register allocation for GHC when f/d is not specified in the… (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155910/new/

https://reviews.llvm.org/D155910

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll

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