[PATCH] D153234: [RISCV] Add codegen for Zfbfmin instructions

[Jun Sha via Phabricator via llvm-commits]

joshua-arch1 updated this revision to Diff 541308.
joshua-arch1 added a comment.

Use the FPR16 register class for bf16 instructions


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153234/new/

https://reviews.llvm.org/D153234

Files:
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfbfmin.ll

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