[PATCH] D153234: [RISCV] Add codegen for Zfbfmin instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:453
 // Moves (no conversion)
 def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
----------------
The patterns need to be duplicated for bf16. I think it accidentally works now because the type type profile says they only take f16 types so tablegen optimized out the checks.

We need to relax the types in the type constraints and add new patterns.

```
def SDT_RISCVFMV_H_X                                                             
    : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;              
def SDT_RISCVFMV_X_EXTH                                                          
    : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153234/new/

https://reviews.llvm.org/D153234