[PATCH] D155502: [RISCV] Do not use F registers if zvfh/f/d is not specified in the architecture

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD updated this revision to Diff 541183.
eopXD added a comment.

Let the compiler check for available GPR-s before hitting the spec.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155502/new/

https://reviews.llvm.org/D155502

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D155502.541183.patch
Type: text/x-patch
Size: 7916 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230717/8d9c9335/attachment.bin>