[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 541134.
luke added a comment.

Add patterns for rotl using vror.vi with negated immediate
Use uimm6


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155439/new/

https://reviews.llvm.org/D155439

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

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