[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:257
 
+defm : VPatBinarySDNode_VV_VX<rotl, "PseudoVROL">;
+defm : VPatBinarySDNode_VV_VX_VI<rotr, "PseudoVROR", uimm5>;
----------------
What about rotl by immediate using vror.vi with SEW-rotateamt?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:258
+defm : VPatBinarySDNode_VV_VX<rotl, "PseudoVROL">;
+defm : VPatBinarySDNode_VV_VX_VI<rotr, "PseudoVROR", uimm5>;
+
----------------
vror has a uimm6.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155439/new/

https://reviews.llvm.org/D155439