[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3006
 
-bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {
+template <unsigned Bits>
+constexpr inline bool selectVSplatUimm(SDValue N, SDValue &SplatVal,
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Don't template this, pass the value as an argument. There show be a form of `isUInt` that takes an argument.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155439/new/

https://reviews.llvm.org/D155439