[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
luke added reviewers: craig.topper, 4vtomat, reames, fakepaper56, frasercrmck.
Herald added subscribers: jobnoorman, asb, pmatos, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
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Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay.
Herald added a project: LLVM.

These correspond to ROTL/ROTR nodes


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155439

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

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