[PATCH] D155284: [GlobalISel] Fix infinite loop in reassociation combine
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 05:20:40 PDT 2023
foad updated this revision to Diff 540370.
foad added a comment.
Update test.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155284/new/
https://reviews.llvm.org/D155284
Files:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -march=amdgcn -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_reassoc_infinite_loop
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+
+ ; CHECK-LABEL: name: test_reassoc_infinite_loop
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: SI_RETURN implicit $vgpr0
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 1
+ %3:_(s1) = G_ICMP intpred(eq), %1(s32), %1
+ %4:_(s32) = G_SELECT %3(s1), %2, %1
+ %5:_(s32) = COPY %4(s32)
+ %6:_(s32) = G_ADD %0, %5
+ %7:_(s32) = G_ADD %6, %2
+ $vgpr0 = COPY %7(s32)
+ SI_RETURN implicit $vgpr0
+...
Index: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4475,7 +4475,8 @@
Register OpLHSLHS = OpLHSDef->getOperand(1).getReg();
Register OpLHSRHS = OpLHSDef->getOperand(2).getReg();
- if (isConstantOrConstantSplatVector(*MRI.getVRegDef(OpLHSRHS), MRI)) {
+ if (isConstantOrConstantSplatVector(*MRI.getVRegDef(OpLHSRHS), MRI) &&
+ !isConstantOrConstantSplatVector(*MRI.getVRegDef(OpLHSLHS), MRI)) {
if (isConstantOrConstantSplatVector(*OpRHSDef, MRI)) {
// (Opc (Opc X, C1), C2) -> (Opc X, (Opc C1, C2))
MatchInfo = [=](MachineIRBuilder &B) {
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