[PATCH] D155216: [RISCV] Add initial SDNode patterns for unary zvbb instructions

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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This patch adds pseudos and SDNode patterns for vbrev.v, vrev8.v, vclz.v,
vctz.v and vcpop.v.
I've only added them for integer element types so far since we're lacking tests
for floats.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155216

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

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