[PATCH] D154857: [RISCV] In RISCVRVVInitUndef, optimize case where entire register is undef

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:210
 
-    if (false && Info.UsedLanes == ~Info.DefinedLanes) {
-      unsigned RegClassID = getVRLargestSuperClass(MRI->getRegClass(Reg))->getID();
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Is this the correct base line? The `if (false` looks suspicious


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154857/new/

https://reviews.llvm.org/D154857