[PATCH] D154857: [RISCV] In RISCVRVVInitUndef, optimize case where entire register is undef

[Philip Reames via Phabricator via llvm-commits]

reames updated this revision to Diff 539117.
reames added a comment.

Fix base revision.

On reflection, I'm not sure this patch is worthwhile.  My original intent was to simplify a deeper change to the algorithm by factoring out test changes into a pre-commit, but after spending a bunch of time exploring that deeper change yesterday, it turned out to be less profitable and a lot more risky than I'd expected.  Given that, I'm not planning on pursuing it, and this patch is somewhat weakly justified on it's own merits.

I'll leave it up for a few days in case anyone wants to approve, but if this gets stuck in review, I'll probably just abandon the patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154857/new/

https://reviews.llvm.org/D154857

Files:
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir

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