[PATCH] D154857: [RISCV] In RISCVRVVInitUndef, optimize case where entire register is undef

[Philip Reames via Phabricator via llvm-commits]

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The sub-register logic is correct for an entirely undef register, but needlessly complicated.  We can do a single undef pseudo instead.

Note that the undef being adjusted in the test is the pass thru, which doesn't actually require the non-overlap constraint.  However, the sub-register logic doesn't include the special case for passthru operands that the implicit_def logic does.  However, the logic in implicit_def logic also looks suspect, so this isn't as simple as just copying it across.  We really should merge the two code paths, and I'm looking into that.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154857

Files:
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir

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