[PATCH] D153721: [RISCV] Add support for XCVsimd extension in CV32E40P

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


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Comment at: llvm/docs/RISCVUsage.rst:278
+``XCVsimd``
+  LLVM implements `version 1.3.1 of the Core-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.
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I think per the discussion in another thread, this should actually be 1.0.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153721/new/

https://reviews.llvm.org/D153721