[PATCH] D154744: [RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly

[Craig Topper via Phabricator via llvm-commits]

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Some instructions treat x0 as a special encoding rather than as a
value of 0. Since we don't parse the inline assembly to know what
the instruction is, chooser the safest option of never using x0.

Fixes #63747.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154744

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/inline-asm.ll


Index: llvm/test/CodeGen/RISCV/inline-asm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm.ll
+++ llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -29,6 +29,33 @@
   ret i32 %2
 }
 
+; Don't allow 'x0' for 'r'. Some instructions have a different behavior when
+; x0 is encoded.
+define i32 @constraint_r_zero(i32 %a) nounwind {
+; RV32I-LABEL: constraint_r_zero:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, %hi(gi)
+; RV32I-NEXT:    lw a0, %lo(gi)(a0)
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_r_zero:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, %hi(gi)
+; RV64I-NEXT:    lw a0, %lo(gi)(a0)
+; RV64I-NEXT:    li a1, 0
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+  %1 = load i32, ptr @gi
+  %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 0, i32 %1)
+  ret i32 %2
+}
+
 define i32 @constraint_i(i32 %a) nounwind {
 ; RV32I-LABEL: constraint_i:
 ; RV32I:       # %bb.0:
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15845,7 +15845,7 @@
       // TODO: Support fixed vectors up to XLen for P extension?
       if (VT.isVector())
         break;
-      return std::make_pair(0U, &RISCV::GPRRegClass);
+      return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
     case 'f':
       if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)
         return std::make_pair(0U, &RISCV::FPR16RegClass);


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