[PATCH] D154687: [RISCV] Narrow types of index operand matched pattern (shl (zext), C).
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 7 00:16:01 PDT 2023
craig.topper added inline comments.
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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10634
+ SDValue Src = N0.getOperand(0);
+ MVT SrcVT = Src.getSimpleValueType();
+ unsigned SrcElen = SrcVT.getScalarSizeInBits();
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Can we guarantee Src has an MVT type here? The intrinsic could be used with an illegal zext input type before type legalization.
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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10635
+ MVT SrcVT = Src.getSimpleValueType();
+ unsigned SrcElen = SrcVT.getScalarSizeInBits();
+ unsigned ShAmtV = ShAmt.getZExtValue();
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Can SrcElen be 1 if the input is a mask type before we legalize zero_extend?
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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12982
+ Ops[4] = V;
+ return DAG.getNode(N->getOpcode(), SDLoc(N), N->getVTList(), Ops);
+ }
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I think this should be getMemIntrinsicSDNode to preserve the mem operand.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D154687/new/
https://reviews.llvm.org/D154687
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