[PATCH] D154687: [RISCV] Narrow types of index operand matched pattern (shl (zext), C).
Yeting Kuo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 6 23:34:14 PDT 2023
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(shl (zext to iXLenVec), C) is a possible pattern in auto-vectorized code for
indexed loads/stores. But extending to iXLen might be too aggressive, RVV
indexed load/store instructions zero extend their indexed operand to XLEN.
The patch tries to narrow the type of the zero extension. It's benefit to
decrease register pressure.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D154687
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
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