[PATCH] D154687: [RISCV] Narrow types of index operand matched pattern (shl (zext), C).

Yeting Kuo via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 6 23:34:14 PDT 2023


fakepaper56 created this revision.
fakepaper56 added reviewers: craig.topper, reames, frasercrmck, rogfer01, luke.
Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
fakepaper56 requested review of this revision.
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay.
Herald added a project: LLVM.

(shl (zext to iXLenVec), C) is a possible pattern in auto-vectorized code for
indexed loads/stores. But extending to iXLen might be too aggressive, RVV
indexed load/store instructions zero extend their indexed operand to XLEN.
The patch tries to narrow the type of the zero extension. It's benefit to
decrease register pressure.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154687

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D154687.538005.patch
Type: text/x-patch
Size: 75106 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230707/4c8e8561/attachment.bin>


More information about the llvm-commits mailing list