[llvm] ee34fa0 - [RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 5 19:36:30 PDT 2023
Author: Craig Topper
Date: 2023-07-05T19:35:13-07:00
New Revision: ee34fa00327bece839dc580b16cdae0bfa75c1e6
URL: https://github.com/llvm/llvm-project/commit/ee34fa00327bece839dc580b16cdae0bfa75c1e6
DIFF: https://github.com/llvm/llvm-project/commit/ee34fa00327bece839dc580b16cdae0bfa75c1e6.diff
LOG: [RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
This pattern started showing up more after D151284
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/calling-conv-half.ll
llvm/test/CodeGen/RISCV/copysign-casts.ll
llvm/test/CodeGen/RISCV/fpclamptosat.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 25d376c9ecfbeb..0bfa277f083df0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12408,6 +12408,15 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue(N, 0);
break;
}
+ case RISCVISD::FMV_W_X_RV64: {
+ // If the input to FMV_W_X_RV64 is just FMV_X_ANYEXTW_RV64 the the
+ // conversion is unnecessary and can be replaced with the
+ // FMV_X_ANYEXTW_RV64 operand.
+ SDValue Op0 = N->getOperand(0);
+ if (Op0.getOpcode() == RISCVISD::FMV_X_ANYEXTW_RV64)
+ return Op0.getOperand(0);
+ break;
+ }
case RISCVISD::FMV_X_ANYEXTH:
case RISCVISD::FMV_X_ANYEXTW_RV64: {
SDLoc DL(N);
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/calling-conv-half.ll
index dfc91ca145ad5e..fc53f70186b763 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-half.ll
@@ -97,8 +97,6 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: mv s0, a0
-; RV64-LP64F-NEXT: fmv.x.w a0, fa0
-; RV64-LP64F-NEXT: fmv.w.x fa0, a0
; RV64-LP64F-NEXT: call __extendhfsf2 at plt
; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64F-NEXT: addw a0, s0, a0
@@ -306,8 +304,6 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: mv s0, a7
-; RV64-LP64F-NEXT: fmv.x.w a0, fa0
-; RV64-LP64F-NEXT: fmv.w.x fa0, a0
; RV64-LP64F-NEXT: call __extendhfsf2 at plt
; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64F-NEXT: addw a0, s0, a0
@@ -613,8 +609,6 @@ define i32 @caller_half_ret() nounwind {
; RV64-LP64F-NEXT: addi sp, sp, -16
; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: call callee_half_ret at plt
-; RV64-LP64F-NEXT: fmv.x.w a0, fa0
-; RV64-LP64F-NEXT: fmv.w.x fa0, a0
; RV64-LP64F-NEXT: call __extendhfsf2 at plt
; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/copysign-casts.ll b/llvm/test/CodeGen/RISCV/copysign-casts.ll
index d93f998eb3c165..931db00d06f8b6 100644
--- a/llvm/test/CodeGen/RISCV/copysign-casts.ll
+++ b/llvm/test/CodeGen/RISCV/copysign-casts.ll
@@ -178,8 +178,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0
-; RV64IFD-NEXT: fmv.x.w a0, fa1
-; RV64IFD-NEXT: fmv.w.x fa0, a0
+; RV64IFD-NEXT: fmv.s fa0, fa1
; RV64IFD-NEXT: call __extendhfsf2 at plt
; RV64IFD-NEXT: fcvt.d.s fa5, fa0
; RV64IFD-NEXT: fsgnj.d fa0, fs0, fa5
@@ -293,8 +292,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.s fs0, fa0
-; RV64IFD-NEXT: fmv.x.w a0, fa1
-; RV64IFD-NEXT: fmv.w.x fa0, a0
+; RV64IFD-NEXT: fmv.s fa0, fa1
; RV64IFD-NEXT: call __extendhfsf2 at plt
; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
index 854bfaa3e702a2..e3684af4f4de2b 100644
--- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -395,8 +395,6 @@ define i32 @stest_f16i32(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 524288
@@ -446,8 +444,6 @@ define i32 @utesth_f16i32(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64-NEXT: li a1, -1
@@ -506,8 +502,6 @@ define i32 @ustest_f16i32(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: li a1, -1
@@ -914,8 +908,6 @@ define i16 @stest_f16i16(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 8
@@ -967,8 +959,6 @@ define i16 @utesth_f16i16(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
@@ -1016,8 +1006,6 @@ define i16 @ustest_f16i16(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
@@ -1727,8 +1715,6 @@ define i64 @stest_f16i64(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: call __fixsfti at plt
; RV64-NEXT: li a2, -1
@@ -1806,8 +1792,6 @@ define i64 @utesth_f16i64(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: call __fixunssfti at plt
; RV64-NEXT: snez a1, a1
@@ -1884,8 +1868,6 @@ define i64 @ustest_f16i64(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: call __fixsfti at plt
; RV64-NEXT: slti a2, a1, 1
@@ -2289,8 +2271,6 @@ define i32 @stest_f16i32_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 524288
@@ -2336,8 +2316,6 @@ define i32 @utesth_f16i32_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64-NEXT: li a1, -1
@@ -2389,8 +2367,6 @@ define i32 @ustest_f16i32_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: li a1, -1
@@ -2785,8 +2761,6 @@ define i16 @stest_f16i16_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 8
@@ -2836,8 +2810,6 @@ define i16 @utesth_f16i16_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64-NEXT: sext.w a0, a0
@@ -2885,8 +2857,6 @@ define i16 @ustest_f16i16_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
@@ -3526,8 +3496,6 @@ define i64 @stest_f16i64_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: call __fixsfti at plt
; RV64-NEXT: li a2, -1
@@ -3603,8 +3571,6 @@ define i64 @utesth_f16i64_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: call __fixunssfti at plt
; RV64-NEXT: snez a1, a1
@@ -3664,8 +3630,6 @@ define i64 @ustest_f16i64_mm(half %x) {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: fmv.x.w a0, fa0
-; RV64-NEXT: fmv.w.x fa0, a0
; RV64-NEXT: call __extendhfsf2 at plt
; RV64-NEXT: call __fixsfti at plt
; RV64-NEXT: mv a2, a1
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 28cbbcaf87c56c..099ea86aa53508 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -145,8 +145,6 @@ define i16 @fcvt_si_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -458,8 +456,6 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: feq.s a0, fa0, fa0
; RV64ID-NEXT: lui a1, %hi(.LCPI1_0)
@@ -667,8 +663,6 @@ define i16 @fcvt_ui_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -926,8 +920,6 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: lui a0, %hi(.LCPI3_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
@@ -1092,8 +1084,6 @@ define i32 @fcvt_w_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -1323,8 +1313,6 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.w.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
@@ -1486,8 +1474,6 @@ define i32 @fcvt_wu_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -1641,8 +1627,6 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: seqz a1, a0
@@ -1905,8 +1889,6 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
@@ -2106,8 +2088,6 @@ define i64 @fcvt_l_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -2564,8 +2544,6 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
@@ -2893,8 +2871,6 @@ define i64 @fcvt_lu_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -3218,8 +3194,6 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
@@ -5181,8 +5155,6 @@ define float @fcvt_s_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64ID-NEXT: addi sp, sp, 16
@@ -5542,8 +5514,6 @@ define double @fcvt_d_h(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.d.s fa0, fa0
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -6346,8 +6316,6 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -6663,8 +6631,6 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: feq.s a0, fa0, fa0
; RV64ID-NEXT: lui a1, %hi(.LCPI32_0)
@@ -6871,8 +6837,6 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -7136,8 +7100,6 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: lui a0, %hi(.LCPI34_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI34_0)(a0)
@@ -7316,8 +7278,6 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -7625,8 +7585,6 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: feq.s a0, fa0, fa0
; RV64ID-NEXT: neg a0, a0
@@ -7830,8 +7788,6 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -8083,8 +8039,6 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fmv.w.x fa5, zero
; RV64ID-NEXT: fmax.s fa5, fa0, fa5
@@ -8362,8 +8316,6 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
@@ -8631,8 +8583,6 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT: fmv.x.w a0, fa0
-; RV64ID-NEXT: fmv.w.x fa0, a0
; RV64ID-NEXT: call __extendhfsf2 at plt
; RV64ID-NEXT: fcvt.w.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
diff --git a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
index 35d75a02ddd554..71c4d7dd2764fd 100644
--- a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
@@ -176,8 +176,6 @@ define half @sin_f16(half %a) nounwind {
; RV64IFD-LP64D: # %bb.0:
; RV64IFD-LP64D-NEXT: addi sp, sp, -16
; RV64IFD-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-LP64D-NEXT: fmv.x.w a0, fa0
-; RV64IFD-LP64D-NEXT: fmv.w.x fa0, a0
; RV64IFD-LP64D-NEXT: call __extendhfsf2 at plt
; RV64IFD-LP64D-NEXT: call sinf at plt
; RV64IFD-LP64D-NEXT: call __truncsfhf2 at plt
@@ -193,8 +191,6 @@ define half @sin_f16(half %a) nounwind {
; RV64IF-LP64F: # %bb.0:
; RV64IF-LP64F-NEXT: addi sp, sp, -16
; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-LP64F-NEXT: fmv.x.w a0, fa0
-; RV64IF-LP64F-NEXT: fmv.w.x fa0, a0
; RV64IF-LP64F-NEXT: call __extendhfsf2 at plt
; RV64IF-LP64F-NEXT: call sinf at plt
; RV64IF-LP64F-NEXT: call __truncsfhf2 at plt
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