[llvm] ee72359 - [X86] Remove unnecessary VPDPB/VPDPW overrides from AlderlakeP model

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-07-05T12:27:42+01:00
New Revision: ee72359c658f5e6759f9bbd2964bf5fc86e679ef

URL: https://github.com/llvm/llvm-project/commit/ee72359c658f5e6759f9bbd2964bf5fc86e679ef
DIFF: https://github.com/llvm/llvm-project/commit/ee72359c658f5e6759f9bbd2964bf5fc86e679ef.diff

LOG: [X86] Remove unnecessary VPDPB/VPDPW overrides from AlderlakeP model

Noticed while trying to resurrect D138359 - the overrides matched the base class schedule WriteVecIMul definition

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86SchedAlderlakeP.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 2cf5c6fe9f46af..eb7dcfc6108bf2 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -2304,13 +2304,6 @@ def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
 def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
 def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
 
-def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
-  let Latency = 13;
-  let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup265], (instregex "^VPDP(BU|WS)SD((SY)?)rm$",
-                                                "^VPDP(BU|WS)SD(S|Y)rm$")>;
-
 def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 2, 1];
   let Latency = 10;