[PATCH] D154447: [PowerPC] Improve code gen for vector add

Tue Jul 4 13:48:41 PDT 2023

nemanjai added a comment.

In D154447#4472054 <https://reviews.llvm.org/D154447#4472054>, @stefanp wrote:

> Unfortunately, this isn't just a case of adding:
>
>   def : Pat<(v2i64 (shl v2i64:$vA, (v2i64 (immEQOneV)))),
>             (v2i64 (VADDUDM $vA, $vA))>;
>
> like the others but I think it may be worth doing.

Yeah, this is because we don't have a way of materializing the `<1, 1>` vector so we end up with a constant pool load. We can provide custom legalization:
`setOperationAction(ISD::SHL, MVT::v2i64, Custom);` for Power8 and up where we would just leave the node alone if it's a shift by 1.

> At this point maybe just add the test case and we can deal with the issue at a later date.

I agree this can be done in a follow-up patch.

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D154447