[llvm] d229184 - [PowerPC] Add DFP quantum adjustment instruction definitions and MC tests
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 4 12:10:41 PDT 2023
Author: Lei Huang
Date: 2023-07-04T15:10:37-04:00
New Revision: d22918484e7769fd8667a64a7df662b6de6bde6c
URL: https://github.com/llvm/llvm-project/commit/d22918484e7769fd8667a64a7df662b6de6bde6c
DIFF: https://github.com/llvm/llvm-project/commit/d22918484e7769fd8667a64a7df662b6de6bde6c.diff
LOG: [PowerPC] Add DFP quantum adjustment instruction definitions and MC tests
Add td definitions and asm/disasm tests for the quantum adjustment
instructions in ISA 3.1 section 5.6.4
Reviewed By: stefanp
Differential Revision: https://reviews.llvm.org/D154369
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrDFP.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrDFP.td b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
index 01193c55c4aa28..3459e625b787c6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrDFP.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
@@ -56,6 +56,39 @@ let isCompare = 1 in {
def DCMPOQ : XForm_17<63, 130, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
"dcmpoq $BF, $RA, $RB", IIC_FPCompare>;
}
-}
-}
+
+// 5.6.4 DFP Quantum Adjustment Instructions
+defm DQUAI: Z23Form_TE5_FRTB5_RMC2r<59, 67, (outs f8rc:$FRT),
+ (ins s5imm:$TE, f8rc:$FRB, u2imm:$RMC),
+ "dquai", "$TE, $FRT, $FRB, $RMC", []>;
+defm DQUAIQ: Z23Form_TE5_FRTB5_RMC2r<63, 67, (outs fpairrc:$FRT),
+ (ins s5imm:$TE, fpairrc:$FRB, u2imm:$RMC),
+ "dquaiq", "$TE, $FRT, $FRB, $RMC", []>;
+defm DQUA: Z23Form_FRTAB5_RMC2r<59, 3, (outs f8rc:$FRT),
+ (ins f8rc:$FRA, f8rc:$FRB, u2imm:$RMC),
+ "dqua", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DQUAQ: Z23Form_FRTAB5_RMC2r<63, 3, (outs fpairrc:$FRT),
+ (ins fpairrc:$FRA, fpairrc:$FRB, u2imm:$RMC),
+ "dquaq", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DRRND: Z23Form_FRTAB5_RMC2r<59, 35, (outs f8rc:$FRT),
+ (ins f8rc:$FRA, f8rc:$FRB, u2imm:$RMC),
+ "drrnd", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DRRNDQ: Z23Form_FRTAB5_RMC2r<63, 35, (outs fpairrc:$FRT),
+ (ins f8rc:$FRA, fpairrc:$FRB, u2imm:$RMC),
+ "drrndq", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DRINTX: Z23Form_FRTB5_R1_RMC2r<59, 99, (outs f8rc:$FRT),
+ (ins u1imm:$R, f8rc:$FRB, u2imm:$RMC),
+ "drintx", "$R, $FRT, $FRB, $RMC", []>;
+defm DRINTXQ: Z23Form_FRTB5_R1_RMC2r<63, 99, (outs fpairrc:$FRT),
+ (ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
+ "drintxq", "$R, $FRT, $FRB, $RMC", []>;
+defm DRINTN: Z23Form_FRTB5_R1_RMC2r<59, 227, (outs f8rc:$FRT),
+ (ins u1imm:$R, f8rc:$FRB, u2imm:$RMC),
+ "drintn", "$R, $FRT, $FRB, $RMC", []>;
+defm DRINTNQ: Z23Form_FRTB5_R1_RMC2r<63, 227, (outs fpairrc:$FRT),
+ (ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
+ "drintnq", "$R, $FRT, $FRB, $RMC", []>;
+
+} // mayRaiseFPException
+} // hasNoSchedulingInfo
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index dfa9fe1cfd668c..a52cf68ba26fbe 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -2171,6 +2171,54 @@ class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Inst{31} = 0;
}
+class Z23Form_FRTAB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> FRT;
+ bits<5> FRA;
+ bits<5> FRB;
+ bits<2> RMC;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isRecordForm
+
+ let Inst{6 - 10} = FRT;
+ let Inst{11 - 15} = FRA;
+ let Inst{16 - 20} = FRB;
+ let Inst{21 - 22} = RMC;
+ let Inst{23 - 30} = xo;
+ let Inst{31} = RC;
+}
+
+class Z23Form_TE5_FRTB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, asmstr, pattern> {
+ bits<5> TE;
+ let FRA = TE;
+}
+
+class Z23Form_FRTB5_R1_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> FRT;
+ bits<1> R;
+ bits<5> FRB;
+ bits<2> RMC;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isRecordForm
+
+ let Inst{6 - 10} = FRT;
+ let Inst{11 - 14} = 0;
+ let Inst{15} = R;
+ let Inst{16 - 20} = FRB;
+ let Inst{21 - 22} = RMC;
+ let Inst{23 - 30} = xo;
+ let Inst{31} = RC;
+}
+
//===----------------------------------------------------------------------===//
// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
// stuff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 25b2f9b1942fa3..d95fc9b36a47fd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1085,6 +1085,53 @@ multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
}
}
+multiclass
+ Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME
+ : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern>, RecFormRel;
+ let Defs = [CR0] in
+ def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ []>, isRecordForm, RecFormRel;
+ }
+}
+
+multiclass
+ Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern>, RecFormRel;
+ let Defs = [CR1] in
+ def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ []>, isRecordForm, RecFormRel;
+ }
+}
+
+multiclass
+ Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern>, RecFormRel;
+ let Defs = [CR1] in
+ def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ []>, isRecordForm, RecFormRel;
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// END OF MULTICLASS DEFINITIONS
+//===----------------------------------------------------------------------===//
+
//===----------------------------------------------------------------------===//
// PowerPC Instruction Definitions.
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
index 963ded45eb066b..1b6d034896b11a 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -59,3 +59,63 @@
# CHECK: dcmpoq 2, 6, 4
0xfd 0x06 0x21 0x04
+
+# CHECK: dquai 15, 8, 4, 3
+0xed 0x0f 0x26 0x86
+
+# CHECK: dquai. 15, 8, 4, 3
+0xed 0x0f 0x26 0x87
+
+# CHECK: dquaiq 15, 8, 4, 3
+0xfd 0x0f 0x26 0x86
+
+# CHECK: dquaiq. 15, 8, 4, 3
+0xfd 0x0f 0x26 0x87
+
+# CHECK: dqua 7, 15, 4, 2
+0xec 0xef 0x24 0x06
+
+# CHECK: dqua. 7, 15, 4, 2
+0xec 0xef 0x24 0x07
+
+# CHECK: dquaq 6, 14, 4, 2
+0xfc 0xce 0x24 0x06
+
+# CHECK: dquaq. 6, 14, 4, 2
+0xfc 0xce 0x24 0x07
+
+# CHECK: drrnd 8, 12, 6, 2
+0xed 0x0c 0x34 0x46
+
+# CHECK: drrnd. 8, 12, 6, 2
+0xed 0x0c 0x34 0x47
+
+# CHECK: drrndq 8, 12, 6, 2
+0xfd 0x0c 0x34 0x46
+
+# CHECK: drrndq. 8, 12, 6, 2
+0xfd 0x0c 0x34 0x47
+
+# CHECK: drintx 1, 8, 10, 3
+0xed 0x01 0x56 0xc6
+
+# CHECK: drintx. 0, 8, 10, 3
+0xed 0x00 0x56 0xc7
+
+# CHECK: drintxq 0, 8, 10, 3
+0xfd 0x00 0x56 0xc6
+
+# CHECK: drintxq. 1, 8, 10, 3
+0xfd 0x01 0x56 0xc7
+
+# CHECK: drintn 0, 10, 6, 2
+0xed 0x40 0x35 0xc6
+
+# CHECK: drintn. 1, 10, 6, 2
+0xed 0x41 0x35 0xc7
+
+# CHECK: drintnq 1, 10, 6, 2
+0xfd 0x41 0x35 0xc6
+
+# CHECK: drintnq. 0, 10, 6, 2
+0xfd 0x40 0x35 0xc7
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
index 3032302e37d54a..189ce223a33776 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
@@ -62,3 +62,63 @@
# CHECK-BE: dcmpoq 2, 6, 4 # encoding: [0xfd,0x06,0x21,0x04]
# CHECK-LE: dcmpoq 2, 6, 4 # encoding: [0x04,0x21,0x06,0xfd]
dcmpoq 2, 6, 4
+# CHECK-BE: dquai 15, 8, 4, 3 # encoding: [0xed,0x0f,0x26,0x86]
+# CHECK-LE: dquai 15, 8, 4, 3 # encoding: [0x86,0x26,0x0f,0xed]
+ dquai 15, 8, 4, 3
+# CHECK-BE: dquai. 15, 8, 4, 3 # encoding: [0xed,0x0f,0x26,0x87]
+# CHECK-LE: dquai. 15, 8, 4, 3 # encoding: [0x87,0x26,0x0f,0xed]
+ dquai. 15, 8, 4, 3
+# CHECK-BE: dquaiq 15, 8, 4, 3 # encoding: [0xfd,0x0f,0x26,0x86]
+# CHECK-LE: dquaiq 15, 8, 4, 3 # encoding: [0x86,0x26,0x0f,0xfd]
+ dquaiq 15, 8, 4, 3
+# CHECK-BE: dquaiq. 15, 8, 4, 3 # encoding: [0xfd,0x0f,0x26,0x87]
+# CHECK-LE: dquaiq. 15, 8, 4, 3 # encoding: [0x87,0x26,0x0f,0xfd]
+ dquaiq. 15, 8, 4, 3
+# CHECK-BE: dqua 7, 15, 4, 2 # encoding: [0xec,0xef,0x24,0x06]
+# CHECK-LE: dqua 7, 15, 4, 2 # encoding: [0x06,0x24,0xef,0xec]
+ dqua 7, 15, 4, 2
+# CHECK-BE: dqua. 7, 15, 4, 2 # encoding: [0xec,0xef,0x24,0x07]
+# CHECK-LE: dqua. 7, 15, 4, 2 # encoding: [0x07,0x24,0xef,0xec]
+ dqua. 7, 15, 4, 2
+# CHECK-BE: dquaq 6, 14, 4, 2 # encoding: [0xfc,0xce,0x24,0x06]
+# CHECK-LE: dquaq 6, 14, 4, 2 # encoding: [0x06,0x24,0xce,0xfc]
+ dquaq 6, 14, 4, 2
+# CHECK-BE: dquaq. 6, 14, 4, 2 # encoding: [0xfc,0xce,0x24,0x07]
+# CHECK-LE: dquaq. 6, 14, 4, 2 # encoding: [0x07,0x24,0xce,0xfc]
+ dquaq. 6, 14, 4, 2
+# CHECK-BE: drrnd 8, 12, 6, 2 # encoding: [0xed,0x0c,0x34,0x46]
+# CHECK-LE: drrnd 8, 12, 6, 2 # encoding: [0x46,0x34,0x0c,0xed]
+ drrnd 8, 12, 6, 2
+# CHECK-BE: drrnd. 8, 12, 6, 2 # encoding: [0xed,0x0c,0x34,0x47]
+# CHECK-LE: drrnd. 8, 12, 6, 2 # encoding: [0x47,0x34,0x0c,0xed]
+ drrnd. 8, 12, 6, 2
+# CHECK-BE: drrndq 8, 12, 6, 2 # encoding: [0xfd,0x0c,0x34,0x46]
+# CHECK-LE: drrndq 8, 12, 6, 2 # encoding: [0x46,0x34,0x0c,0xfd]
+ drrndq 8, 12, 6, 2
+# CHECK-BE: drrndq. 8, 12, 6, 2 # encoding: [0xfd,0x0c,0x34,0x47]
+# CHECK-LE: drrndq. 8, 12, 6, 2 # encoding: [0x47,0x34,0x0c,0xfd]
+ drrndq. 8, 12, 6, 2
+# CHECK-LE: drintx 0, 8, 10, 3 # encoding: [0xc6,0x56,0x00,0xed]
+# CHECK-BE: drintx 0, 8, 10, 3 # encoding: [0xed,0x00,0x56,0xc6]
+ drintx 0, 8, 10, 3
+# CHECK-LE: drintx. 1, 8, 10, 3 # encoding: [0xc7,0x56,0x01,0xed]
+# CHECK-BE: drintx. 1, 8, 10, 3 # encoding: [0xed,0x01,0x56,0xc7]
+ drintx. 1, 8, 10, 3
+# CHECK-LE: drintxq 1, 8, 10, 3 # encoding: [0xc6,0x56,0x01,0xfd]
+# CHECK-BE: drintxq 1, 8, 10, 3 # encoding: [0xfd,0x01,0x56,0xc6]
+ drintxq 1, 8, 10, 3
+# CHECK-LE: drintxq. 0, 8, 10, 3 # encoding: [0xc7,0x56,0x00,0xfd]
+# CHECK-BE: drintxq. 0, 8, 10, 3 # encoding: [0xfd,0x00,0x56,0xc7]
+ drintxq. 0, 8, 10, 3
+# CHECK-LE: drintn 1, 10, 6, 2 # encoding: [0xc6,0x35,0x41,0xed]
+# CHECK-BE: drintn 1, 10, 6, 2 # encoding: [0xed,0x41,0x35,0xc6]
+ drintn 1, 10, 6, 2
+# CHECK-LE: drintn. 0, 10, 6, 2 # encoding: [0xc7,0x35,0x40,0xed]
+# CHECK-BE: drintn. 0, 10, 6, 2 # encoding: [0xed,0x40,0x35,0xc7]
+ drintn. 0, 10, 6, 2
+# CHECK-LE: drintnq 0, 10, 6, 2 # encoding: [0xc6,0x35,0x40,0xfd]
+# CHECK-BE: drintnq 0, 10, 6, 2 # encoding: [0xfd,0x40,0x35,0xc6]
+ drintnq 0, 10, 6, 2
+# CHECK-LE: drintnq. 1, 10, 6, 2 # encoding: [0xc7,0x35,0x41,0xfd]
+# CHECK-BE: drintnq. 1, 10, 6, 2 # encoding: [0xfd,0x41,0x35,0xc7]
+ drintnq. 1, 10, 6, 2
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